EDA技术（机械）实验报告--定时器.docx
实验报告（计算机类）开课学院及实验室：实验时间：年月曰学生姓名学号成绩学生所在学院年级/专业/班2012/自动化/西华理1课程名称EDA技术（机械）课程代码实验项目名称定时器项目代码十指导教师项目学分一、实验目的1. .了解VHDL语言编程方法，学会熟练运用quartus软件2. 了解定时器工作原理3. 了解如何使用VHDL设计一个定时器二、内容与设计思想1 .定时器是计数器和显示器的综合应用。基于VHDL语言，用FPGA实现，硬件简单，性能稳定,可充分体现可编程逻辑器件在数字电路中的优越性。2 .要求;整体清零；最高可定时99min;预置数时以秒速度递增至预定时间，以分速度递减至零。三、使用环境WinXP或Win7QUartUSii编程环境四、核心代码及调试过程定时器设计AAA逻辑功能模块，十进制输出Iibraryieee;useieee.std_Iogic_1164.aII;useieee.std_Iogic_unsigned.all;entityaaaisport(elk,clr,set:instd_logic;aIm:outstd_logic;q1,q:outstd_Iogic_vector(3downto0)；endaaa;architectureaaa_arcofaaaisbeginprocess(cIk)variabIecnt1,cnt:std_Iogic_vector(3downto0);variabIeent:integerrange0to59;beginifcIr='O'thenalm<=,0'ent:=0;cnt1="0000'r;cnt:="0000,1;eIsifcIk,eventandcIk='1,thenifset='0,thenent:=0;ifcnt<"1001"thencnt:=cnt0+1;eIseCnt0:="0000”；ifcnt1<,1001"thencnt1:=cnt1+1;eIsecnt1="0000;endif;endif;eIseifcnt<59thenent:=cnt+1;eIseent:=0;ifcnt0>>,0000"thenCnt0:=Cnto-I;ifcnt1=,0000"andcnt0=,0000"thenalm<=,;endif;eIseCntO=Io01”；ifcnt1>,0000"thencnt1:=cnt1-1;eIsecnt1:=M1001"endif;endif;endif;CflC aim dr q13.0 set q03. .0endif;endif;mstq<=cnt;q1<=cnt1;endprocess;endaaa_arc;二一CH模块，对应片选信号送出要显示的相应数据Iibraryieee;useieee.std_Iogic_1164.aII;entitychisport(seI:instd_logic;a1,a:instd_Iogic_vector(3downto0);q:outstd_Iogic_vector(3downtoO)；endch;architecturech_arcofchisbeginprocess(seI.a,a1)beginifsel='O'thenq<=a;eIseq<=a1;endif;endprocess;endch_arc;DlSP模块Iibraryieee;useieee.std_Iogic_1164.aII;entitydispisport(a:instd_Iogic_vector(3downtoO);q:outstd_Iogic_vector(6downtoO)；enddisp;architecturedisp_arcofdispisbeginprocess(a)begincaseaswhen,0000,=>q<=,011111,when,000,=>q<="0000110"when"0010"=>q<="1011011"when"001,=>q<="1001111"when,0100"=>q<=,1100110"when"010,=>q<=,110110,when,0110"=>q<=,111110,when-011,=>q<=,000011,when,1000,=>q<=,111111,when,100,=>q<=,110111,whenothers=>q<="0000000"endcase;endprocess;总体框图:enddisp_arc;五、总结六、附录（仿真结果）
